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?2013-2014 peregrine semiconductor corp. all rights reserved. page 1 of 12 document no. doc-32314-2 | www.psemi.com features ?? four symmetric 50 ? absorptive ports ?? high isolation ?? 45 db @ 3 ghz ?? 39 db @ 6 ghz ?? 31 db @ 8 ghz ?? low insertion loss ?? 0.8 db @ 3 ghz ?? 1.0 db @ 6 ghz ?? 1.2 db @ 8 ghz ?? high linearity ?? 58 dbm iip3 @ 8 ghz ?? 110 dbm iip2 @ 8 ghz ?? 1.8v control logic compatible ?? esd performance ?? 2 kv hbm on all pins ?? 100v mm on all pins ?? 1 kv cdm on all pins PE42441 ultracmos ? sp4t rf switch 10 mhz ? 8 ghz product description the PE42441 is a harp? technology-enhanced absorptive sp4t rf switch designed for use in various switching applications spanning multiple markets including wireless infrastructure, broadband, and test & measurement. this switch has four symmetric rf ports and delivers low insertion loss and exceptional isolation. an on-chip cmos decode logic facilitates a two-pin low voltage cmos control interface. in addition, no external blocking capacitors are required if 0 vdc is present on rf ports. the PE42441 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate. peregrine?s harp? technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos ? process, offering the performance of gaas with the economy and integration of conventional cmos. figure 1. functional diagram rf4 rf1 rf3 cmos control/ driver and esd v dd v1 rf2 v2 esd 50 esd 50 esd 50 esd 50 rf c figure 2. package type 32-lead 5x5 mm lga product specification doc-51532
document no. doc-32314-2 | ultracmos ? rfic solutions page 2 of 12 ?2013-2014 peregrine semiconductor corp. all rights reserved. PE42441 product specification table 1. electrical specifications @ 25c, v dd = 3.3v (z s = z l = 50 ? ), unless otherwise specified parameter path condition min typ max unit operating frequency 10 mhz 8 ghz insertion loss rfc-rfx 10 mhz ? 3000 mhz 3000 mhz ? 6000 mhz 6000 mhz ? 7500 mhz 7500 mhz ? 8000 mhz 0.8 1.0 1.1 1.2 1.1 1.3 1.5 1.6 db db db db isolation (active port to terminated port) rfx-rfx 10 mhz ? 3000 mhz 3000 mhz ? 6000 mhz 6000 mhz ? 7500 mhz 7500 mhz ? 8000 mhz 40 34 27 25 45 39 32 31 db db db db isolation (common port to active port) rfc-rfx 10 mhz ? 3000 mhz 3000 mhz ? 6000 mhz 6000 mhz ? 7500 mhz 7500 mhz ? 8000 mhz 40 28 24 21 45 33 29 27 db db db db return loss (active port) rfx 10 mhz ? 3000 mhz 3000 mhz ? 6000 mhz 6000 mhz ? 7500 mhz 7500 mhz ? 8000 mhz 23 18 17 16 db db db db return loss (terminated port) rfx 10 mhz ? 3000 mhz 3000 mhz ? 6000 mhz 6000 mhz ? 7500 mhz 7500 mhz ? 8000 mhz 18 13 11 10 db db db db input 0.1 db compression point 1 rfc-rfx 10 mhz ? 8000 mhz 31 dbm input ip3 rfc-rfx 8000 mhz 58 dbm input ip2 rfc-rfx 8000 mhz 110 dbm switching time 50% ctrl to 90% or 10% rf 5 8 s settling time 50% ctrl to 0.05 db final value (?40 to +85c) rising edge 50% ctrl to 0.05 db final value (?40 to +85c) falling edge 14 15 18 45 s s return loss (common port) rfx 10 mhz ? 3000 mhz 3000 mhz ? 6000 mhz 6000 mhz ? 7500 mhz 7500 mhz ? 8000 mhz 23 18 14 13 db db db db note 1: the input 0.1db compression point is a linearity figure of merit. refer to table 3 for the operating rf input power (50 ? )
?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-32314-2 | www.psemi.com PE42441 page 3 of 12 product specification figure 3. pin configuration (top view) pin # pin name description 1, 3-6, 8, 9-12, 14-17, 19-22, 24-26, 28, 31, 32 gnd ground 2 rf4 1 rf port 7 rf2 1 rf port 13 rfc 1 rf common 18 rf1 1 rf port 23 rf3 1 rf port 27 v dd supply voltage 29 v1 digital control logic input 1 30 v2 digital control logic input 2 pad gnd exposed pad: ground for proper operation table 2. pin descriptions note 1: rf pins 2, 7, 13, 18, and 23 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper operation if the 0v dc requirement is met table 3. operating ranges parameter symbol min typ max unit supply voltage v dd 3.0 3.3 3.55 v digital input high (v1, v2) v ih 1.2 1.5 v dd v digital input low (v1, v2) v il 0 0 0.4 v digital input current i ctrl 1 a rf input power, cw 1 10 mhz ? 8 ghz p max,cw see fig. 4 dbm rf input power into terminated ports, cw 10 mhz ? 8 ghz p max,term +20 dbm operating temperature range t op ?40 +85 c supply current i dd 90 160 a notes: 1. 100% duty cycle (?40 to +85c, 1:1 vswr) g n d g n d g n d g n d g n d r f c g n d g n d g n d g n d g n d v 2 v 1 g n d v d d g n d table 4. absolute maximum ratings parameter/condition symbol min max unit supply voltage v dd -0.3 4 v digital input voltage (v1, v2) v ctrl 4 v maximum input power 10 mhz ? 8 ghz p max,abs see fig. 4 dbm storage temperature range t st ?60 +150 c esd voltage hbm 1 , all pins v esd,hbm 2 kv esd voltage mm 2 , all pins v esd,mm 100 v esd voltage cdm 3 , all pins v esd,mm 1 kv notes: 1. human body model (mil-std 883 method 3015.7) 2. machine model (jedec jesd22-a115-a) 3. charged device model (jedec jesd22-c101) exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
document no. doc-32314-2 | ultracmos ? rfic solutions page 4 of 12 ?2013-2014 peregrine semiconductor corp. all rights reserved. PE42441 product specification electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. switching frequency the PE42441 has a maximum 25 khz switching rate. switching frequency describes the time duration between switching events. switching time is the time duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. table 5. truth table state v1 v2 rf1 on 0 0 rf2 on 1 0 rf3 on 0 1 rf4 on 1 1 spurious performance the typical spurious performance of the PE42441 is -144 dbm. moisture sensitivity level the moisture sensitivity level rating for the PE42441 in the 32-lead 5x5 mm lga package is msl3. figure 4. power de-rating curve vs temperature 26.5 27 27.5 28 28.5 29 29.5 30 30.5 31 31.5 \ 40 0 25 50 85 input ? power ? (dbm) ambient ? temperature ? (c) maximum input power (pmax, abs) rf input power, cw (pmax, cw)
?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-32314-2 | www.psemi.com PE42441 page 5 of 12 product specification figure 7. insertion loss vs. v dd (rfc-rfx) figure 6. insertion loss vs. temp (rfc-rfx) figure 5. insertion loss (rfc-rfx) typical performance data @ 25c and v dd = 3.3v unless otherwise specified
document no. doc-32314-2 | ultracmos ? rfic solutions page 6 of 12 ?2013-2014 peregrine semiconductor corp. all rights reserved. PE42441 product specification figure 11. active port return loss vs. v dd figure 10. active port return loss vs. temp typical performance data @ 25c and v dd = 3.3v, unless otherwise specified figure 8. rfc port return loss vs. temp figure 9. rfc port return loss vs. v dd
?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-32314-2 | www.psemi.com PE42441 page 7 of 12 product specification figure 15. isolation vs. v dd (rfx-rfx) figure 14. isolation vs. temp (rfx-rfx) typical performance data @ 25c and v dd = 3.3v, unless otherwise specified figure 12. terminated port return loss vs. temp figure 13. terminated port return loss vs. v dd
document no. doc-32314-2 | ultracmos ? rfic solutions page 8 of 12 ?2013-2014 peregrine semiconductor corp. all rights reserved. PE42441 product specification 0 20 40 60 80 100 120 10.0e+6 100.0e+6 1.0e+9 10.0e+9 linearity [dbm] frequency [hz] nominal iip3 [dbm] nominal iip2 [dbm] figure 18. linearity performance figure 16. isolation vs. temp (rfc-rfx) figure 17. isolation vs. v dd (rfc-rfx) typical performance data @ 25c and v dd = 3.3v, unless otherwise specified
?2013-2014 peregrine semiconductor corp. all rights reserved. document no. doc-32314-2 | www.psemi.com PE42441 page 9 of 12 product specification figure 19. evaluation board layouts prt-28605 evaluation kit the sp4t switch ek board was designed to ease customer evaluation of peregrine?s PE42441. the rf common port is connected through a 50 ? transmission line via the top sma connector, j1. rf1, rf2, rf3 and rf4 are connected through 50 ? transmission lines via sma connectors j2, j4, j3 and j5, respectively. a through 50 ? transmission is available via sma connectors j6 and j7. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a four metal layer material with a total thickness of 62 mils. the dual clad top rf layer is rogers ro4003 material with an 8 mil rf core and er = 3.55. the middle layers provide ground for the transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 15 mils, trace gaps of 10 mils, and metal thickness of 2.1 mils.
document no. doc-32314-2 | ultracmos ? rfic solutions page 10 of 12 ?2013-2014 peregrine semiconductor corp. all rights reserved. PE42441 product specification through li ne j6 j1 j4 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j8 header 14 j2 c1 22p f c2 22p f j7 r3 0 ohm 1 gnd 2 rf4 3 gnd 4 gnd 5 gnd 6 gnd 7 rf2 8 gnd 17 gnd 18 rf1 19 gnd 20 gnd 21 gnd 22 gnd 23 rf3 24 gnd 25 gnd 26 gnd 27 vdd 28 gnd 29 v1 30 v2 31 gnd 32 gnd 9 gnd 10 gnd 11 gnd 12 gnd 13 rfc 14 gnd 15 gnd 16 gnd u1 pe4244 1 j5 j3 r2 1m r4 0 ohm r5 0 ohm r6 dni c3 22p f r1 1m c5 0.1uf c6 0.1uf r7 0ohm rfc rf1 rf3 rf2 rf4 figure 20. evaluation board schematic doc-32327
?2013-2014 peregrine semiconductor corp. all rights reserved. page 11 of 12 document no. doc-32314-2 | www.psemi.com top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features 5.00 5.00 pin #1 corner 3.030.05 3.030.05 3.50 0.4350.050 (x32) 0.50 0.34 (x32) 0.260.05 (x32) 0.24 0.70 0.940.06 1 8 9 16 17 24 25 32 3.50 0.34 (x32) 3.08 3.08 4.90 4.90 0.50 (x28) detail a detail b 0.485 (x32) (x28) 0.11 0.10 0.10 0.535 0.04 0.15 detail a detail b 0.424 45 chamfer figure 21. package drawing figure 22. marking specifications doc-01877 42441 yyww zzzzzz doc-51207 = pin 1 indicator yyww = date code, last two digits of the year and work week zzzzzz = six digits of the lot number
document no. doc-32314-2 | ultracmos ? rfic solutions page 12 of 12 ?2013-2014 peregrine semiconductor corp. all rights reserved. PE42441 product specification tape feed direction notes: 1. 10 sprocket hole pitch cumulative tolerance 0.02 2. camber not to exceed 1 mm in 100 mm 3. material: ps + c 4. ao and bo measured as indicated 5. ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole ao = 5.25 0.05 mm bo = 5.25 0.05 mm ko = 1.1 0.05 mm figure 23. tape and reel drawing table 6. ordering information order code description package shipping method PE42441a-z PE42441 sp4t rf switch green 32-lead 5x5 mm lga 3000 units / t&r ek42441-01 PE42441 evaluation ki t evaluation kit 1 / box advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

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